Semiconductor integrated circuit device and manufacturing method of that

ABSTRACT

A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a technique for manufacturing asemiconductor integrated circuit device. The invention particularlyrelates to a technique effective for application to a CSP (chip sizepackage) that is electrically connected via a metal wire between a bumpelectrode disposed on a chip and an electrode part before rearrangement.

[0002] Along with reduction in electric and electronic apparatuses insize, the reduction of semiconductor integrated circuit devices used inthe apparatuses for them have also been progressed in both size andthickness. The CSP means a general name of a package having a sizeequivalent to or slightly larger than the size of a semiconductor chip,and this CSP has been practically used as a package capable of realizingthe reduction in sizes and thickness.

[0003] A metal wire is used to connect this CSP, a gap between anelectrode part before rearrangement (for example, a part called abonding pad), being a part of top-layer wires arranged in asemiconductor chip and a bump electrode being an external connectionterminal.

[0004] There are following methods for performing the above-mentionedconnection, for example. A passivation film and a polyimide film on thetop-layer wires are selectively removed by etching, and thereby exposingthe electrode part before rearrangement. Thereafter, a copper (Cu) filmis deposited by a sputtering method on the passivation film and theelectrode part before rearrangement to perform a pattering. By thismethod, a copper wire is formed to extend from the electrode part beforerearrangement to a bump electrode formation area. A method like this isdisclosed in, for example, Japanese Patent Laid-open No. 8-340002.

[0005] There is also a method of forming a wire-shaped projectionextending from the electrode part before rearrangement to the bumpelectrode formation area by a bonding machine. Such a method isdisclosed in, for example, U.S. Pat. No. 5,476,211.

[0006] Meanwhile, as a technique for encapsulating a semiconductor chip,there has been investigated a technique of forming an encapsulationlayer by using photocurable components for curing the resin with opticalenergy. According to this technique, after forming an encapsulationlayer using the photocurable components, a solder paste is chargedtherein. Then, a solder bump is formed on this paste. This technique isdisclosed in, for example, Japanese Patent Laid-open No. 8-293509.

[0007] However, in the above-described methods, it is difficult todevelop materials as sputtering durability is required in forming copperwires on a polyimide film that is used as a stress relaxation layer.Further, it is difficult to reduce cost of manufacturing the copperwires as the manufacture includes many processes.

[0008] On the other hand, in the case of forming the wire-shapedprojection by using the bonding machine, there is a limit to respectivepitches between terminals because the terminals are formed mechanically.Further, a short circuit occurs easily between the terminals as theterminals are exposed outside.

[0009] Further, in the above method using the photocurable components,both metal wiring part (solder paste part) and encapsulation layer seemto have insufficient stress relaxing force.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide a method ofmanufacturing a semiconductor integrated circuit device having a stressrelaxing force and being capable of forming both a metal wiring part anda guide layer in a relatively simple process and in high precision byutilizing a photocurable resin. The guide layer also works as aprotection film for protecting a metal wire.

[0011] The above object and new features of the present invention willbecome apparent from description of the present specification and theappended drawings.

[0012] Among the aspects disclosed in the present invention, somerepresentative aspects are briefly explained as follows.

[0013] (1) According to a method of manufacturing a semiconductorintegrated circuit device of the present invention, a photocurable resinlayer is formed on an insulation film and an electrode part beforerearrangement on a semiconductor substrate. A laser beam is irradiatedonto a periphery of a metal wiring formation scheduled area that extendsfrom the electrode part before rearrangement to a bump electrode contactarea. By scanning, the photocurable resin is cured, and a guide layer isformed. Then, a metal wire is formed by plating in a hollow-shaped partalong this guide layer.

[0014] (2) A metal wire may be formed by forming a metal seed layer forelectroplating on the electrode part before rearrangement and byperforming electroplating.

[0015] (3) An aperture larger than the bump electrode contact area maybe formed in the guide layer.

[0016] (4) And an induction hole may be formed in a part of a lower areaof the guide layer.

[0017] (5) Further, according to a method of manufacturing asemiconductor integrated circuit device of the present invention, aphotocurable resin layer is formed on an insulation film and anelectrode part before rearrangement on a semiconductor substrate. Alaser beam is irradiated onto metal wiring formation scheduled area thatextends from the electrode part before rearrangement to a bump electrodecontact area. By scanning, the photocurable resin is cured. Then, asurface of this cured resin is plated, thereby forming a metal wire.

[0018] (6) Further, according to a method of manufacturing asemiconductor integrated circuit device of the present invention, aphotocurable resin layer is formed on a packaging substrate on which achip having a semiconductor integrated circuit is mounted. Then, a laserbeam is irradiated onto this layer, and by scanning, an opticalwaveguide, a signal path like a high-frequency transmission path, or apassage for a liquid substance is formed.

[0019] (7) A semiconductor integrated circuit device of the presentinvention has a metal wire that extends from an electrode part beforerearrangement to a bump electrode contact area, and a protection layerthat is formed around the metal wire by curing a photocurable resin.

[0020] (8) A semiconductor integrated circuit device of the presentinvention has a cured resin part that extends from an electrode partbefore rearrangement to a bump electrode contact area and that is formedby curing a photocurable resin, and a metal wiring part formed aroundthe cured resin part.

[0021] (9) A semiconductor integrated circuit device of the presentinvention has a packaging substrate on which a chip having asemiconductor integrated circuit is mounted, and an optical waveguide, asignal path like a high-frequency transmission path, or a passage for aliquid substance made of a cured resin part that is formed by curing aphotocurable resin.

[0022] According to the above means, a photocurable resin is utilized,and the resin near the metal wiring formation area that extends from theelectrode part before rearrangement to the bump electrode is cured,thereby forming a metal wiring guide layer and a protection film. Themetal wire is formed, thereafter. Therefore, it is possible to form thismetal wiring part and the metal wiring guide layer that also works as aprotection film, in a relatively simple process and with high precision.

[0023] Further, as the metal wire covered by the guide layer andprotection film, it is possible to relax the external stress to themetal wire.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 1 of the present invention.

[0025]FIG. 2 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 1 of the invention.

[0026]FIG. 3 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 1 of the invention.

[0027]FIG. 4 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 1 of the invention.

[0028]FIG. 5 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 1 of the invention.

[0029]FIG. 6 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 1 of the invention.

[0030]FIG. 7 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 2 of the invention.

[0031]FIG. 8 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0032]FIG. 9 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0033]FIG. 10 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0034]FIG. 11 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0035]FIG. 12 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0036]FIG. 13 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0037]FIG. 14 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0038]FIG. 15 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0039]FIG. 16 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 2 of the invention.

[0040]FIG. 17 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 3 of the invention.

[0041]FIG. 18 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 3 of the invention.

[0042]FIG. 19 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0043]FIG. 20 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0044]FIG. 21 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0045]FIG. 22 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0046]FIG. 23 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0047]FIG. 24 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention;

[0048]FIG. 25 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0049]FIG. 26 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 3 of the invention.

[0050]FIG. 27 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 4 of the invention.

[0051]FIG. 28 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 4 of the invention.

[0052]FIG. 29 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 4 of the invention.

[0053]FIG. 30 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 4 of the invention.

[0054]FIG. 31 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 4 of the invention.

[0055]FIG. 32 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 4 of the invention.

[0056]FIG. 33 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 5 of the invention.

[0057]FIG. 34 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 5 of the invention.

[0058]FIG. 35 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 5 of the invention.

[0059]FIG. 36 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 5 of the invention.

[0060]FIG. 37 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to the embodiment 5 of the invention.

[0061]FIG. 38(a) is a cross-sectional view of a cured resin part takenalong a line A-A′ in FIG. 28.

[0062]FIG. 38(b) is a cross-sectional view of a cured resin part takenalong a line A-A′ in FIG. 28.

[0063]FIG. 39(a) is a cross-sectional view of a cured resin part takenalong a line B-B′ in FIG. 28 respectively.

[0064]FIG. 39(b) is a cross-sectional view of a cured resin part takenalong a line B-B′ in FIG. 28 respectively.

[0065]FIG. 39(c) is a cross-sectional view of a cured resin part takenalong a line B-B′ in FIG. 28 respectively.

[0066]FIG. 40 is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 8 of the invention.

[0067]FIG. 41 is a top plane view of a key part of a substrate showing amethod of manufacturing a semiconductor integrated circuit devicerelating to embodiment 9 of the invention.

[0068]FIG. 42 is a cross-sectional view of a pantograph shape part takenalong a line A-A′ in FIG. 41.

[0069]FIG. 43 is a top plane view of a key part of a substrate showing amethod of manufacturing a semiconductor integrated circuit devicerelating to the embodiment 9 of the invention.

[0070]FIG. 44 is a cross-sectional view of a wiring layer taken along aline A-A′ in FIG. 43.

[0071]FIG. 45 (a) is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 10 of the invention.

[0072]FIG. 45(b) is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 10 of the invention.

[0073]FIG. 45(c) is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 10 of the invention.

[0074]FIG. 45(d) is a cross-sectional view of a key part of a substrateshowing a method of manufacturing a semiconductor integrated circuitdevice relating to embodiment 10 of the invention.

[0075]FIG. 46(a) is a diagram showing one example of a cross section ofa cured resin part 104 shown in FIG. 45(b).

[0076]FIG. 46(b) is a perspective view of a substrate provided with acooling pipe.

[0077]FIG. 47 is a cross-sectional view of a key part of a substrateshowing a pre-processing of a method of manufacturing a semiconductorintegrated circuit device relating to the embodiments of the invention;and

[0078]FIG. 48 is a cross-sectional view of a key part of a substrateshowing a post-processing of a method of manufacturing a semiconductorintegrated circuit device relating to the embodiments of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] Embodiments of the present invention will be explained in detailbelow with reference to the drawings. In explaining the embodiments,components having the same function will be denoted by the samereference numbers or symbols, and repetitive explanation of thecomponents will be omitted.

[0080] (Embodiment 1)

[0081] A method of manufacturing a semiconductor integrated circuitdevice, which is embodiment 1 of the present invention, will beexplained with reference to FIG. 1 to FIG. 6 in sequence.

[0082] As shown in FIG. 1, a protection layer 2 (an insulation film)consisting of a passivation film and a polyimide resin or the like isformed on a semiconductor substrate (hereinafter to be simply referredto as a substrate) 1. This protection layer 2 is formed on top-layerwires 3 that is formed on the substrate 1. Parts of the protection layer2 are removed so as to expose respective parts of these top-layer wiresas electrode parts before rearrangement BP. While not shown in FIG. 1,elements (semiconductor elements) of such a MISFET (Metal InsulatorSemiconductor Field Effect Transistors) or the like as to constitute amemory, a microcomputer, or the like are formed on the substrate 1, andare connected to the top-layer wires via a plurality of wiring layers.FIG. 47 shows one example of this arrangement. As shown in FIG. 47, bymeans of a normal MOS device process, MISFETQns are formed on an activearea of the substrate 1 on which a diffusion area 472 is formed, thatis, on an area on which a field oxide film 473 is not formed. A siliconoxide film 474 is formed on this MISFETQn. Then, parts of the siliconoxide film 474 on source and drain areas of the MISFETQn are removed,thereby forming contact holes therein. Further, an Al (aluminum) film475 is deposited in the contact holes and on the silicon oxide film 474by a sputtering method. Thereafter, a patterning is carried out on theAl film 475 by dry etching. Similarly, a silicon oxide film 476 isformed on the Al film 475 and the silicon oxide film 474. Thereafter,contact holes are formed in the silicon oxide film 476 to provide Alwires 477. Further, a silicon oxide film 478 is formed on the Al wires477 and the silicon oxide film 476, and thereafter, contact holes areformed in the silicon oxide film 478 to provide Al wires 3 (thetop-layer wires). As explained above, it is possible to obtain amulti-wiring structure by alternately forming a silicon oxide film andAl wires thereon. On the top-layer wires 3, an inorganic passivationfilm 2 a and an organic passivation film 2 b (the protection film 2)like a polyimide resin layer thereon are formed. By selectively removingthese films, respective parts of the top-layer wires 3 are exposed asthe electrode parts before rearrangement BP, as explained above.

[0083] Next, as shown in FIG. 2, a photocurable resin is coated on theprotection layer 2 and the electrode part before rearrangement BP,thereby forming a photocurable resin layer 4 thereon. For forming thisphotocurable resin layer 4, there are used a method of adhering aphotocurable resin formed in a tape shape onto the substrate or a methodof screen printing. It is also possible to use a method of accommodatinga liquid photocurable resin in a vessel and fixing the substrate in avessel. For the photocurable resin, it is possible to use urethaneacrylate, photosensitive polyimide, silicon resin, fluorine-containedresin, etc.

[0084] Next, as shown in FIG. 3, a laser beam 5 is irradiated into thephotocurable resin layer 4, thereby bringing about curing reaction ofthe photocurable resin layer 4 at a light-focusing part FP of this beam.The photocurable resin layer 4 at the peripheral portion of a metalwiring formation area (a broken-line part shown in FIG. 3) describedlater is cured by scanning the light-focusing part FP in the peripheralportion of this metal wiring formation area from the respectiveelectrodes part before rearrangement BP to respective bump electrodecontact areas BA. There are various methods for this scanning, includinga method of scanning along a spiral line on the peripheral portion ofthe metal wiring formation area. For the laser beam, there can be usedan excimer laser, an electron beam, X-rays, and ultraviolet rays.

[0085] Next, uncured portions of the photocurable resin layer 4 areremoved. As a result, cylindrical cured resin parts 6 (guide layers)having the metal wiring formation area formed in a hollow shape,respectively, are provided, as shown in FIG. 4. These cured resin parts6 become the guide layers for protecting metal wires when the metalwires described later are formed. After forming the metal wires, thesecured resin parts 6 become the protection layers for relaxing the stressapplied to the metal wires.

[0086] Next, the substrate 1 is dipped into a copper nonelectrodeplating liquid, and copper is grown inside each of the cured resin parts6, thereby forming a copper wire 7 (the metal wire) having a diameter of3 to 10 μm and extending from each of the electrode parts beforerearrangement BP to each of the bump electrode contact areas BA, asshown in FIG. 5.

[0087] Further, as shown in FIG. 6, a solder bump 8 (a bump electrode)is formed on the respective bump electrode contact areas BAcorresponding to the copper wire 7 by a ball transfer method, a screenprinting method, or a solder plating (tinning) method or the like.Thereafter, the substrate 1 in a wafer state is died and divided into aplurality of chips. The chips are packaged as shown in FIG. 48, forexample. In other words, the chips are mounted facedown on a packagingsubstrate 481, and the bump electrodes 8 are reflow soldered. Anunder-fill resin may be filled between the chips and the packagingsubstrate 481.

[0088] As explained above, according to the present embodiment, byutilizing a photocurable resin, resin near the metal wiring formationarea, which extends from the respective electrode parts beforerearrangement BP to the respective bump electrode contact areas BA, iscured, thereby obtaining the guide layers 6 for the metal wires. Andthen, the metal wires 7 are formed. Therefore, it is possible to formboth the metal wires 7 and the cured resin parts 6 working as both theguide layers and the protection films for protecting these metal wirescan be formed in relatively simple processes and with high precision.Further, according to the present embodiment, it is possible to form theS-shaped metal wires 7 easily, and it is possible to relax stressgenerated between the chips and the packaging substrate 481.

[0089] (Embodiment 2)

[0090] Next, a method of manufacturing a semiconductor integratedcircuit device, which is embodiment 2 of the present invention, will beexplained with reference to FIG. 7 to FIG. 16 in sequence.

[0091] As shown in FIG. 7, a protection layer 2 (an insulation film)consisting of an inorganic passivation film and an organic passivationfilm like a polyimide resin is formed on a substrate 1, in a similarmanner to that of the embodiment 1. Parts of the protection layer 2 areremoved so as to expose a part of each of these top-layer wires 3 aseach of the electrode parts before rearrangement BP.

[0092] Next, as shown in FIG. 8, a seed layer 21 (a metal seed layer)for electroplating is formed on the other parts of the protection layer2 and the electrode parts before rearrangement BP. Further, as shown inFIG. 9, a resist film 22 is formed on the seed layer 21 for electrolyticplating, and then parts of the resist film 22 being arranged on andcorresponding to the respective electrode parts before rearrangement BPis removed by photolithography.

[0093] Hereafter, as shown in FIG. 10, a photocurable resin is coated onthe resist film 22 and the electrode part before rearrangement BP,thereby forming a photocurable resin layer 4, in a similar manner tothat of the first embodiment. Thereafter, as shown in FIG. 11, thephotocurable resin layer 4 at the peripheral portion of a metal wiringformation area (a broken-line part shown in FIG. 11) is cured byscanning the light-focusing part FP with a laser beam 5 on theperipheral portion of this metal wiring formation area from therespective electrode parts before rearrangement BP to respective bumpelectrode contact areas BA.

[0094] Next, respective uncured portions of the photocurable resin layer4 are removed to provide respective cylindrical cured resin parts 6(guide layers) having the metal wiring formation area formed in a hollowshape, as shown in FIG. 12.

[0095] Next, copper is grown inside each of the cured resin parts 6 byelectroplating, thereby forming copper wires 7 (the metal wires) thatextends from the respective electrode parts before rearrangement BP tothe respective bump electrode contact areas BA, as shown in FIG. 13.

[0096] Thereafter, the resist film 22 is removed as shown in FIG. 14,and the seed layer 21 for electroplating is removed by light etching, asshown in FIG. 15.

[0097] Further, as shown in FIG. 16, a solder bump 8 (a bump electrode)is formed on the each of bump electrode contact areas BA in the copperwires 7 by a ball transfer method or a screen printing method or thelike. It is also possible to form the solder bump 8 by electroplating.In the case of forming the solder bump 8 by electroplating, solder maybe grown after the above-mentioned copper wires 7 (metal wires) isformed.

[0098] Thereafter, the substrate 1 in a wafer state is died, therebybeing divided into a plurality of chips, and the chips are packaged.

[0099] As explained above, according to the present embodiment, the seedlayer 21 for electroplating is formed on the respective electrode partsbefore rearrangement BP, and the copper wires 7 is formed byelectroplating. Therefore, the growth speed of the plating becomes fast,so that it becomes possible to carry out a prompt processing for formingthe copper wires. Particularly, this method is suitable for forming along slender copper wire.

[0100] (Embodiment 3)

[0101] A method of manufacturing a semiconductor integrated circuitdevice, which is embodiment 3 of the present invention, will beexplained with reference to FIG. 17 to FIG. 26 in sequence.

[0102] As shown in FIG. 17, a protection layer 2 (an insulation film)consisting of an inorganic passivation film and an organic passivationfilm like a polyimide resin is formed on a substrate 1, in a similarmanner to that of the embodiment 1. Parts of the protection layer 2 havebeen removed so as to expose parts of the top-layer wires 3 as electrodeparts before rearrangement BP.

[0103] Next, as shown in FIG. 18, a seed layer 21 for electroplating isformed on the protection layer 2 and the electrode parts beforerearrangement BP. Further, as shown in FIG. 19, a resist film 22 isformed on the seed layer 21 for electroplating, and then parts of theresist film 22 being arranged on and corresponding to the electrodeparts before rearrangement BP is removed by photolithography.Thereafter, a photocurable resin layer 4 is coated on the other parts ofthe resist film 22 and the electrode parts before rearrangement BP.

[0104] Next, as shown in FIG. 20, the photocurable resin at theperipheral portion of a metal wiring formation area (a broken-line partshown in FIG. 20) is cured by scanning the light-focusing part FP with alaser beam 5 on the peripheral portion of this metal wiring formationarea from the respective electrode parts before rearrangement BP torespective bump electrode contact are as BA. In this case, the scanningis carried out with such laser beam 5 that respective areas OA largerthan the respective bump electrode contact areas BA become an aperturein the photocurable resin layer 4 cured (FIG. 21).

[0105] Next, uncured portions of the photocurable resin layer 4 areremoved, and then each of cured resin parts 6 (guide layers) in whichthe metal wiring formation area has a hollow shape is provided, as shownin FIG. 21. Each of these cured resin parts 6 has a shape that the areasOA larger than the bump electrode contact areas BA are open,respectively.

[0106] Next, copper is grown inside each of the cured resin parts 6 byelectroplating, thereby forming copper wires 7 (the metal wires) thatextend from the electrode parts before rearrangement BP to the areas OA,as shown in FIG. 22. In this case, when unevenness has occurred on somesurfaces of the copper wires 7, these surfaces are flattened using achemical mechanical polishing (CMP) method, for example.

[0107] Thereafter, the resist film 22 is removed as shown in FIG. 23,and then the seed layer 21 for electroplating is removed by lightetching, as shown in FIG. 24.

[0108] Further, as shown in FIG. 25, an insulation film 31 is formed onthe areas OA arranged on the copper wires 7, and then parts of theinsulation film 31 being on and corresponding to the bump electrodecontact areas BA are removed by etching. For forming this insulationfilm 31, a printing method may be used, or a photocurable resin may beused to form this insulation film again.

[0109] Next, as shown in FIG. 26, solder bumps 8 (bump electrodes) arerespectively formed on the bump electrode contact areas BA by a balltransfer method or by a screen printing method or the like. Thereafter,the substrate 1 in a wafer state is died, thereby being divided into aplurality of chips, and the chips are packaged.

[0110] As explained above, according to the present embodiment, each ofthe cured resin parts 6 is formed so that each of the areas OA includingthe bump electrode contact areas BA has an open shape. Therefore, infollowing electroplating process, a plating liquid is supplied from thisaperture in each of the areas OA, and the growth speed of the platingbecomes fast, so that it becomes possible to reduce the processing time.Even in the case of forming copper wires by nonelectrode plating withoutforming the seed layer 21 for electroplating, if the cured resin parts 6having the same shape are formed, then the plating liquid is suppliedfrom the apertures thereof, and the growth speed of the plating becomesfast.

[0111] (Embodiment 4)

[0112] Next a method of manufacturing a semiconductor integrated circuitdevice, which is embodiment 4 of the present invention will be explainedwith reference to FIG. 27 to FIG. 32 in sequence.

[0113] As shown in FIG. 27, a protection layer 2 (an insulation film)consisting of an inorganic passivation film and an organic passivationfilm like a polyimide resin is formed on a substrate 1, in a similarmanner to that of the first embodiment. Parts of the protection layer 2are removed so as to expose respective parts of top-layer wires 3 as anelectrode parts before rearrangement BP. Of a resist film 41 formed onboth the others of the protection layer 2 and the electrode parts beforerearrangement BP, parts of the resist film 41 being on and correspondingto the electrode parts before rearrangement BP are removed byphotolithography. This resist film 41 is provided for preventing copperwires 7 described later from being closely adhered to the protectionlayer 2.

[0114] Next, a photocurable resin is coated on others of the resist film41 and the electrode parts before rearrangement BP. Then, thephotocurable resin at the peripheral portion of a metal wiring formationarea is cured by scanning a light-focusing part of a laser beam on theperipheral portion of this metal wiring formation area that extends fromthe respective electrode parts before rearrangement BP to respectivebump electrode contact areas BA. In this case, the scanning is carriedout with a laser beam so that apertures 42 (induction holes) are formedon parts of the resist film 41 positioned beneath the bump electrodecontact areas BA (apart of lower areas) (FIG. 28), respectively.

[0115] Next, uncured portions of the photocurable resin layer areremoved, and thereby each of cured resin parts 6 (guide layers) in whichthe metal wiring formation area has a hollow shape is provided, as shownin FIG. 28. This cured resin parts 6 have the apertures 42 (theinduction holes) on the parts of the resist film positioned beneath thebump electrode contact areas BA, respectively.

[0116] Next, copper is grown inside each of the cured resin parts 6 bydipping the substrate 1 into a copper electroplating liquid, as shown inFIG. 29. Thus, copper wires 7 (the metal wires) are formed which thatextend from the electrode parts before rearrangement BP to the bumpelectrode contact areas BA, respectively.

[0117] Thereafter, the resist film 41 is removed as shown in FIG. 30. Asshown in FIG. 32, it is unnecessary to remove the resist film 41 if theresist film is made of a soft material. Further, as shown in FIG. 31,solder bumps 8 (bump electrodes) are respectively formed on the bumpelectrode contact areas BA by a ball transfer method, a screen printingmethod or the like. Thereafter, the substrate 1 in a wafer state isdied, thereby being divided into a plurality of chips, and the chips arepackaged.

[0118] As explained above, according to the present embodiment, thecured resin parts 6 are formed to have the apertures (induction holes)42 on corresponding parts of the resin film 41 positioned beneath thebump electrode contact areas BA, respectively. Therefore, in thenonelectrode plating process, a plating liquid is supplied from therespective apertures 42 therein, and the growth speed of the platingbecomes fast, so that it becomes possible to reduce the processing time.

[0119] (Embodiment 5)

[0120] Next a method of manufacturing a semiconductor integrated circuitdevice, which is embodiment 5 of the present invention, will beexplained with reference to FIG. 33 to FIG. 37 in sequence.

[0121] As shown in FIG. 33, a protection layer 2 (an insulation film)consisting of an inorganic passivation film and an organic passivationfilm like a polyimide resin is formed on a substrate 1, in a similarmanner to that of the first embodiment. Thereafter, parts of theprotection layer 2 are removed so as to expose parts of these top-layerwires 3 as electrode parts before rearrangement BP, respectively. A seedlayer 51 for electroplating is formed on the electrode parts beforerearrangement BP and the other parts of the protection layer 2. Further,a resist film 52 is formed on the seed layer 51 for electroplating.Parts of the resist film 52 being on and corresponding to the electrodeparts before rearrangement BP are removed by photolithography, and partsof the seed layer 51 for electroplating are exposed outside.

[0122] Hereafter, similarly to the embodiment 4, a photocurable resinlayer is formed on both the resist film 52 and the seed layer 51 forelectroplating, which is positioned on the electrode parts beforerearrangement BP. Then, the photocurable resin at the peripheral portionof metal wiring formation area is cured by scanning a light-focusingpart of a laser beam on the peripheral portion of this metal wiringformation area from the respective electrode parts before rearrangementBP to respective bump electrode contact areas BA. In this case, thescanning is carried out with the laser beam so that apertures 53(induction holes) are formed on corresponding parts of the resist film52 positioned beneath the bump electrode contact areas BA (lower areas)(FIG. 34).

[0123] Next, uncured portions of the photocurable resin are removed, andthereby each of cured resin parts 6 (guide layers) in which the metalwiring formation area has a hollow shape is provided, as shown in FIG.34. These cured resin parts 6 have apertures 53 (induction holes) oncorresponding parts of the resist film 52 positioned beneath the bumpelectrode contact areas BA, respectively.

[0124] Next, copper is grown inside each of the cured resin parts 6 byelectroplating, thereby forming copper wires 7 (the metal wires) thatextend from the electrode parts before rearrangement BP to the bumpelectrode contact areas BA, respectively, as shown in FIG. 35.

[0125] Thereafter, the resist film 52 is removed as shown in FIG. 36.Further, the seed layer 51 for electrolytic plating is removed by lightetching, as shown in FIG. 37. Next, a solder bumps 8 (bump electrodes)are respectively formed on the bump electrode contact areas BA by a balltransfer method, by a screen printing method or the like.

[0126] In the case of forming the solder bumps 8 by electroplating,solder may be grown after the copper wires 7 (the metal wires) areformed. Thereafter, the substrate 1 in a wafer state is died, therebybeing divided into a plurality of chips, and the chips are packaged.

[0127] As explained above, according to the present embodiment, the seedlayer 51 for electroplating is formed on each of the electrode partsbefore rearrangement BP, and the copper wires 7 are formed byelectroplating. Therefore, the growth speed of the plating becomes fast.Further, as the cured resin parts 6 have the apertures (the inductionholes) 53 on corresponding parts of the resist film 52 positionedbeneath the bump electrode contact area BA, the plating liquid issupplied from respective apertures 53 therein. As a result, the growthspeed of the plating becomes faster, and it becomes possible to reducethe processing time.

[0128] (Embodiment 6)

[0129] When the Embodiments 1 to 5 in common have the same layout of theelectrode parts before rearrangement as that of the layout of the bumpelectrodes and the same copper wires in shape, it is possible to installan optical system for branching a laser beam into a plurality of beamsand to form a plurality of cured resin parts 6 simultaneously, in orderto increase the throughput of the cured resin parts 6. In this case, theoptical system of the device is designed so that intervals of the laserbeams match pitches between the bump electrodes.

[0130] When the plurality of branched laser beams are used, it ispossible to simultaneously form a plurality of cured resin parts 6 asexplained above. Therefore, it becomes possible to eminently reduce theprocessing time.

[0131] (Embodiment 7)

[0132] Next, each shape of the cured resin parts 6 will be explainedwith reference to FIG. 28 explained in the embodiment 4, and FIGS. 38(a)and 38(b) and FIGS. 39(a) to 39(c). FIGS. 38(a) and 38(b) showcross-sectional views taken along a line A-A′ in FIG. 28, respectively.As shown in FIG. 38(a), each cross section of the cured resin parts 6formed on the resist film 41 taken along the line A-A′ (FIG. 28), canhave a square shape. Further, as shown in FIG. 38(b), each cross sectionof the cured resin parts 6 taken along the line A-A′ (FIG. 28), may havea semicircle shape (an inverse U shape). Further, it is also possible toform each cross section of the cured resin parts 6 in a U shape notshown.

[0133] FIGS. 39(a) to 39(c) show cross-sectional views of the curedresin parts taken along a line B-B′ in FIG. 28, respectively. As shownin FIGS. 39 (a) to 39(c), the cured resin parts 6 are formed to coverthe electrode parts before rearrangement BP and the respective bumpelectrode formation areas BA, respectively. Each cross section of thecured resin parts 6 taken along the line B-B′ (FIG. 28) has such a shapeas to surround the respective electrode parts before rearrangement BPand the respective bump electrode formation areas BA. Further, as shownin FIG. 39(a), it is possible to form the each cross section of thecured resin parts 6 taken along the line B-B′ in a taper shape from therespective electrode parts before rearrangement BP toward the respectivebump electrode formation areas BA. Further, as shown in FIG. 39(b), itis possible to form the each cross section of the cured resin parts 6taken along the line B-B′ in such a shape as to have a narrow partbetween the electrode parts before rearrangement BP and the bumpelectrode formation areas BA. Further, as shown in FIG. 39(c), it isalso possible to form the each cross section of the cured resin parts 6taken along the line B-B′ in such an approximately rectangular shape asto encircle the respective electrode parts before rearrangement BP andthe respective bump electrode formation areas BA.

[0134] The shapes of the cured resin parts 6 are explained above withreference to FIG. 28, FIGS. 38(a) and 38(b) and FIGS. 39(a) to 39(c).Not only in the embodiment 4 but also the embodiment 1, 2, 3 and 5, itis also possible to form the each cross section of the cured resin partsin a similar shape. Each cross section of the cured resin parts 6 in theembodiment 1 is formed in such a semicircle shape (an inverse U shape)as to be explained with reference to FIG. 38(b) . In addition, at thesame time, each cross section of the cured resin parts 6 can have anarrow shape between the electrode parts before rearrangement BP and thebump electrode formation areas BA as explained with reference to FIG.39(c).

[0135] (Embodiment 8)

[0136] Further, it is also possible to provide radiating plates 81 byusing a photocurable resin as shown in FIG. 40. In other words, afterforming the photocurable resin layer on the resist film 52 and theelectrode parts before rearrangement BP of FIG. 33 described in theembodiment 5, the scanning is performed with the laser beam to form thecured resin parts 6. At this time, the laser beam is irradiated onto thephotocurable resin positioned at a portion other than the peripheralportions of the metal wiring formation area, thereby forming the unevensurface portions (81) (FIG. 40). These uneven surface portions playroles of the radiating plates. By forming these uneven surface portions,it is possible to effectively radiate heat created on active elementformation surfaces of the substrate. Further, it is possible to form theradiating plates 81 in the same process as that for forming the curedresin parts 6 that become the guide parts of the metal wires. Therefore,it is possible to obtain the above-mentioned effects in a simpleprocess.

[0137] The method in the present embodiment can also be applied to theEmbodiments 1 to 4 as well as the embodiment 5.

[0138] (Embodiment 9)

[0139] In the Embodiments 1 to 5, the laser beam is irradiated onto thephotocurable resin layer, and each of the cured resin parts 6 (the guidelayers), in which the metal wiring formation area has a hollow shape, isprovided. Then, the copper wires 7 are formed in these hollow-shapedparts. In stead of this, each of the above-mentioned photocurable resinparts can be used as the wiring layer if an electroplating is performedon each surface of the photocurable resin parts, each of which plays arole of a core.

[0140] First, a substrate having a protection layer (an insulation film)that is formed on the top-layer wires and from which each of thetop-layer wires as the electrode parts before rearrangement is exposed,is prepared in a similar manner to that of the embodiment 1. Then, aphotocurable resin layer is formed on the protection layer and theelectrode parts before rearrangement (FIG. 3).

[0141] Next, a laser beam is irradiated onto the photocurable resinlayer, thereby bringing about a curing reaction of the photocurableresin layer at a light-focusing part of this beam. The light-focusingpart is scanned to draw a shape having pantograph-shaped parts 92 and 93crossed each other at a center part CP as shown in FIG. 41 and FIG. 42.

[0142] Next, uncured portions of the photocurable resin are removed. Asa result, cured resin parts 91 having such a shape that thepantograph-shaped parts 92 and 93 cross each other at the center partCP, remain on the respective electrode parts before rearrangement BP.FIG. 41 shows a top plane view of each of the cured resin parts 91. FIG.42 is a cross-sectional view of the pantograph-shaped parts 92 takenalong a line A-A′ of FIG. 41. The pantograph shape part 93 also has asimilar shape.

[0143] Thereafter, activation processing of surfaces of the cured resinparts 91 is carried out. By this processing, cores for growing theplating are formed on the surfaces of the cured resin parts 91. Further,the substrate 1 is dipped into a copper nonelectrode plating liquid,thereby growing copper or gold on the respective surfaces of the curedresin parts 91 and forming a wiring layer on the respective surfaces ofthe cured resin parts. It is necessary to carry out the activationprocessing on only the surfaces of the cured resin parts 91. Therefore,before opening each of the electrode parts before rearrangement, it isnecessary to carry out a water repellent finish on a surface of thesubstrate in advance, or to cover area of the substrate other thanrespective areas corresponding to the electrode parts beforerearrangement, with a resist material.

[0144] As explained above, according to the present embodiment, aphotocurable resin is utilized to form the respective cured resin parts91 on each of the electrode parts before rearrangement BP. Thereafter,metal plating is provided on the respective surfaces of these curedresin parts 91 to form the metal wires. Therefore, it is possible toform the metal wires with high precision and in a relatively simpleprocess.

[0145] In the present embodiment, the respective cured resin parts 91are formed to have the pantograph-shaped parts 92 and 93 crossed at thecenter part CP. In stead of this, it is also possible to provide each ofthe cured resin parts that has a shape extending from the respectiveelectrode parts before rearrangement to the respective bump electrodecontact areas. On the other hand, if the cured resin parts 91 are formedto have the pantograph-shaped parts 92 and 93 crossed at the center partCP as described in the present embodiment, it is possible for the curedresin parts to obtain improved stress durability.

[0146] Further, if a nickel alloy or the like is further plated on asurface of the above-described copper plating or gold plating, it ispossible to reinforce the wiring layer as shown in FIG. 43 and FIG. 44.FIG. 43 is a top plane view of a wiring layer 94 obtained by plating anickel alloy on a metal plating layer, after these metal wires areplated on the surfaces of the cured resin parts 91. FIG. 44 is across-sectional view taken along a line A-A′of FIG. 43.

[0147] (Embodiment 10)

[0148] Further, when this photocurable resin is used, it is possible toeasily form an optical signal transmission path of a semiconductorintegrated circuit device having an optical input/output part.

[0149] Optical input/output parts 101 and an insulation film 102 areformed on the substrate 1 shown in FIG. 45(a). A resin 103 that isphotocurable and thermoset and that is made of a material having adifferent refractive index depending on a curing condition, is coated onthis substrate 1. Next, as shown in FIG. 45(b), a laser beam isirradiated onto an optical waveguide-formation scheduled area, therebybringing about a curing reaction of the photocurable resin at thelight-focusing part. Thus, photocured resin parts 104 are formed. Next,an uncured photocurable resin part 105 is baked to form a thermosetresin part 106 having a different refractive index (FIG. 45(c)). Each ofthe photocured resin parts 104 becomes a waveguide for an opticalsignal. It is also possible to form the thermoset resin part 106 byremoving the uncured photocurable resin part 105 and forming and bakinga different thermosetting resin on the whole surface of the substrate 1.In this case, the resin 103 needs to have only photocurable property.

[0150] According to the present embodiment, it is possible to form anoptical waveguide with less transmission loss than an optical waveguideformed by a known photolithography, for example. In other words, thephotolithography is a method of exposure on the plane, and therefore,the cross section of the optical waveguide has a rectangular shape. Onthe other hand, when the photocurable resin is used as described in thepresent embodiment, it is possible to form the cross section of theoptical waveguide having a circular shape, thereby reducing in thetransmission loss. As a result, it is possible to improve the opticalsignal transmission performance. Further, as compared with the case offixing a separately formed optical fiber on the substrate, there is nodeviation of the optical axis. Therefore, the method of the presentembodiment is suitable for forming a plurality of optical wave-guideshaving high wiring density.

[0151] Further, when a plurality of chips 1 a and 1 b are mounted on apackaging substrate 107 as shown in FIG. 45(d), a resin 103 is coated onthe packaging substrate 107 and the chips 1 a and 1 b. By radiating alaser beam onto the optical waveguide formation scheduled area, thechips 1 a and 1 b can be connected to each other by an optical waveguideconsisting of photocured resin parts 104.

[0152] Further, each of photocured resin parts 104 is formed in acylindrical shape, and a metal plating is provided on an inner part 108thereof, and each outside of the photocured resin parts 104 is set as aground layer 109, as shown in FIG. 46(a). When impedance is matchedbased on this structure, it is possible to form the inner part 108 ofeach of the photocured resin parts 104 as a high-frequency transmissionpath.

[0153] Further, as shown in FIG. 46(b), while each of the photocuredresin parts 104 (only a portion near the optical input/output part isshown in the drawing) is formed, it is possible to simultaneously formpipes 110 for passing through a cooling agent by utilizing aphotocurable resin. Each of these pipes can be used as a passage forpassing through non-analyzed substance or the like to be inspected andanalyzed by semiconductor integrated circuits in the chips, in additionto the cooling agent. Further, the optical wave-guides, thehigh-frequency transmission paths, the pipes for passing through acooling agent, or the like, as shown in the present embodiment, can alsobe formed on the same substrate on which the guide layer shown in theEmbodiments 1 to 8 is formed. As explained in the present invention, ifthe photocurable resin is used, it is possible to form the elements(such as the optical wave-guides, the high-frequency transmission paths,the guide layer for providing a cooling agent or metal wires, etc.) forvarious purposes on the same substrate.

[0154] As mentioned above, while the present invention made by inventorsis explained in detail based on the embodiments, it is needless to saythat the present invention is not limited to the above-mentionedembodiments and can be modified in various ways without departing fromthe scope and spirit of the invention.

[0155] Effects obtained from the representative invention disclosed canbe briefly summarized as follows.

[0156] According to the present invention, a photocurable resin isutilized, and the resin near the metal wiring formation area thatextends from the respective electrode parts before rearrangement to therespective bump electrodes contact area is cured by scanning with alaser beam, thereby forming guides for the metal wires. Thereafter, therespective metal wires are formed. Therefore, it is possible to formthese metal wires and the guide layer that also works as a protectionfilm for each of the metal wires in a relatively simple process and withhigh precision. Further, according to the present invention, it ispossible to form easily the metal wires 7 having an approximately Sshape (or an approximately inverse Z shape) It is also possible to relaxthe stress applied to the bump electrode.

What is claimed is:
 1. A method of manufacturing a semiconductorintegrated circuit device having a metal wire between an electrode partbefore rearrangement being a part of a top-layer wire and a bumpelectrode working as an external terminal, the method comprising stepsof: (a) forming the top-layer wire that extends on a semiconductorsubstrate and an insulation film that is formed on the top-layer wireand that exposes the electrode part before rearrangement being a part ofthe top-layer wire; (b) forming a photocurable resin layer on both theinsulation film and the electrode part before rearrangement; (c)irradiating a laser beam onto a peripheral portion of an area scheduledfor forming the metal wire, which extends from the electrode part beforerearrangement to a contact area of the bump electrode, and curing thephotocurable resin layer by scanning; (d) forming a guide layer made ofthe cured resin part, in which the metal wiring formation scheduled areahas a hollow shape, by removing an uncured portion of the photocurableresin layer; (e) forming the metal wire that extends from the electrodepart before rearrangement to the bump electrode contact area, byperforming plating in a hollow-shaped part along the guide layer; and(f) forming the bump electrode on the bump electrode contact area of themetal wire.
 2. The method of manufacturing a semiconductor integratedcircuit device according to claim 1 , the method further comprising astep of forming a metal seed layer for electroplating on the electrodepart before rearrangement between the step (a) and the step (b), whereinthe plating at the step (e) is electroplating.
 3. A method ofmanufacturing a semiconductor integrated circuit device having a metalwire between an electrode part before rearrangement being a part of atop-layer wire and a bump electrode working as an external terminal, themethod comprising steps of: (a) forming the top-layer wire that extendson a semiconductor substrate, and an insulation film that is formed onthe top-layer wire and that exposes the electrode part beforerearrangement being a part of the top-layer wire; (b) forming aphotocurable resin layer on both the insulation film and the electrodepart before rearrangement; (c) in a peripheral portion of an areascheduled for forming the metal wire, which extends from the electrodepart before rearrangement to a contact are of the bump electrode,irradiating a laser beam onto an area other than the area that includesthe bump electrode contact area and curing the photocurable resin layer;(d) forming a guide layer, in which the metal wiring formation scheduledarea has a hollow shape and has an aperture larger than the bumpelectrode contact area, by removing an uncured portion of thephotocurable resin layer; (e) forming the metal wire that extends fromthe electrode part before rearrangement to the aperture by performingplating in a hollow-shaped part along the guide layer; (f) forming aninsulator film on the aperture of the metal wire; and (g) exposing themetal wire and forming the bump electrode on an exposed part of themetal wire, by removing the insulation film on the bump electrodecontact area of the metal wire by etching.
 4. A method of manufacturinga semiconductor integrated circuit device having a metal wire between anelectrode part before rearrangement being a part of a top-layer wire anda bump electrode working as an external terminal, the method comprisingsteps of: (a) forming the top-layer wire that extends on a semiconductorsubstrate, and an insulation film that is formed on the top-layer wireand that exposes the electrode part before rearrangement being a part ofthe top-layer wire; (b) forming a photocurable resin layer on both theinsulation film and the electrode part before rearrangement; (c)irradiating a laser beam onto an area that excludes a part of a lowerarea in a peripheral part of an area scheduled for forming the metalwire, which extends from the electrode part before rearrangement to acontact area of the bump electrode, and curing the photocurable resinlayer by scanning; (d) forming a guide layer made of the cured resinlayer, which the metal wiring formation scheduled area has a hollowshape, and having an induction hole in a part of the lower area, byremoving an uncured portion of the photocurable resin layer; (e) formingthe metal wire that extends from the electrode part before rearrangementto the bump electrode contact area, by performing plating in ahollow-shaped part along the guide layer; and (f) forming the bumpelectrode on the bump electrode contact area of the metal wire.
 5. Amethod of manufacturing a semiconductor integrated circuit device havinga metal wire between an electrode part before rearrangement being a partof a top-layer wire and a bump electrode working as an externalterminal, the method comprising steps of: (a) forming the top-layer wirethat extends on a semiconductor substrate, and an insulation film thatis formed on the top-layer wire and that exposes the electrode partbefore rearrangement being a part of the top-layer wire; (b) forming aphotocurable resin layer on both the insulation film and the electrodepart before rearrangement; (c) irradiating a laser beam onto aperipheral portion of an area scheduled for forming the metal wire,which extends from the electrode part before rearrangement to a contactarea of the bump electrode, and curing the photocurable resin layer byscanning; (d) forming a cured resin part that extends from the electrodepart before rearrangement to the bump electrode contact area, byremoving an uncured portion of the photocurable resin layer; (e) formingthe metal wire that extends from the electrode part before rearrangementto the bump electrode contact area, by performing plating in a surfaceof the cured resin part; and (f) forming the bump electrode on the bumpelectrode contact area of the metal wire.
 6. The method of manufacturinga semiconductor integrated circuit device according to claim 5 , whereinthe cured resin part has a pantograph shape.
 7. The method ofmanufacturing a semiconductor integrated circuit device according to anyone of claims 1, 3, 4 and 5, wherein the laser beam at the step (c)consists of a plurality of laser beams disposed at an intervalcorresponding to a pitch between the bump electrode and an bumpelectrode adjacent thereto.
 8. The method of manufacturing asemiconductor integrated circuit device according to any one of claims1, 3, and 4, wherein the step (c) includes a step of scanning an areaother than the peripheral part of the metal wiring formation scheduledarea with the laser beam, and the step (d) includes a step of forming aradiating plate in addition to the guide layer made of a cured resin. 9.A method of manufacturing a semiconductor integrated circuit device,comprising steps of: (a) forming a photocurable resin layer on apackaging substrate mounted with a chip having a semiconductorintegrated circuit; (b) irradiating a laser beam onto an area scheduledfor forming a signal path for inputting/outputting a signal to/from thechips, and curing the photocurable resin layer, by scanning; and (c)forming the signal path by removing an uncured portion of thephotocurable resin layer.
 10. The method of manufacturing asemiconductor integrated circuit device according to claim 9 , whereinthe signal path is an optical waveguide.
 11. The method of manufacturinga semiconductor integrated circuit device according to claim 9 , whereinthe signal path is a cylindrical signal path and is also ahigh-frequency transmission path.
 12. A method of manufacturing asemiconductor integrated circuit device, comprising steps of: (a)forming a photocurable resin layer on a packaging substrate mounted witha chip having a semiconductor integrated circuit; (b) irradiating alaser beam onto the photocurable resin layer, and curing thephotocurable resin layer in a cylindrical shape, by scanning; and (c)forming a pipe by removing an uncured portion of the photocurable resinlayer.
 13. The method of manufacturing a semiconductor integratedcircuit device according to claim 12 , wherein the pipe is a passage fora liquid substance.
 14. A semiconductor integrated circuit device havinga metal wire between an electrode part before rearrangement being a partof a top-layer wiring and a bump electrode working as an externalterminal, the semiconductor integrated circuit device comprising: (a) atop-layer wire that extends on a semiconductor substrate; (b) aninsulation film that is formed on the top-layer wire and that exposesthe electrode part before rearrangement as a part of the top-layer wire;(c) a metal wire that extends from the electrode part beforerearrangement to the bump electrode contact area; (d) a protection layerthat is formed around the metal wire by curing a photocurable resin; and(e) a bump electrode formed on the bump electrode contact area of themetal wire.
 15. The semiconductor integrated circuit device according toclaim 14 , wherein the semiconductor integrated circuit device has aplurality of metal wires, and the protection layer is isolatedcorresponding to each of the plurality of metal wires.
 16. Thesemiconductor integrated circuit device according to claim 14 , whereinthe semiconductor integrated circuit device has a metal seed layer forelectroplating between the electrode part before rearrangement and themetal wire.
 17. The semiconductor integrated circuit device according toclaim 14 , wherein an area other than the bump electrode contact area ona surface of the metal wire is covered with other insulation film. 18.The semiconductor integrated circuit device according to claim 14 ,wherein the protection layer has a hole at a lower part thereof.
 19. Thesemiconductor integrated circuit device according to claim 14 , thesemiconductor integrated circuit device further comprising a radiatingplate formed by curing a photocurable resin.
 20. A semiconductorintegrated circuit device having a metal wire between an electrode partbefore rearrangement being a part of a top-layer wire and a bumpelectrode working as an external terminal, the semiconductor integratedcircuit device comprising: (a) a top-layer wire extending on asemiconductor substrate; (b) an insulation film being formed on thetop-layer wire and exposing the electrode part before rearrangement as apart of the top-layer wire; (c) a cured resin part that extends from theelectrode part before rearrangement to the bump electrode contact area,and that is formed by curing a photocurable resin; (d) a metal wiringpart formed around the cured resin part; and (e) a bump electrode formedon the bump electrode contact area of the metal wiring part.
 21. Thesemiconductor integrated circuit device according to claim 20 , whereinthe cured resin part has a pantograph shape.
 22. A semiconductorintegrated circuit device, the device comprising: (a) a packagingsubstrate mounted with a chip having a semiconductor integrated circuit;and (b) a signal path that inputs/outputs a signal to/from the chip, andthat is made of a cured resin part formed by curing a photocurableresin.
 23. The semiconductor integrated circuit device according toclaim 22 , wherein the signal path is an optical waveguide.
 24. Thesemiconductor integrated circuit device according to claim 22 , whereinthe signal path is a cylindrical signal path and is also ahigh-frequency transmission path.
 25. A semiconductor integrated circuitdevice, the device comprising: (a) a packaging substrate mounted with achip having a semiconductor integrated circuit; and (b) a passage pipeformed near the chip and formed in a cylindrical shape by curing aphotocurable resin.